1. Field of the Invention
The present invention relates generally to computers, and more specifically to an apparatus and method for optimizing bus clock speed in a computer.
2. Background of the Related Art
In general, a computer such as a notebook computer can be supplied with its necessary electric energy by either an equipped battery or an AC power line. However, because battery capacity is limited, a notebook cannot be used for more than a few hours if its power is supplied from the equipped battery.
FIG. 1 is a simplified block diagram of a related art notebook. The notebook of FIG. 1 has a CPU 11 conducting ordinary well-known operations and functions; a bridge controller 12 conducting both assistant operations of the CPU 11 and management of memories, a video port, a bus, etc.; a video processor 13 for processing video data and outputting the processed data for video presentation; and a clock generator 10 providing 100 MHz clock 1 for the CPU 11 and the bridge controller 12, and a 66 MHz clock 2 for the video processor 13.
A PLL (Phase Lock Loop) circuit 110 is embedded in the CPU 11. The PLL circuit 110 multiplies the 100 MHz clock 1 from the clock generator 10 differently based on a current power supplying mode. For example, the PLL circuit 110 multiplies the 100 MHz clock by six times to produce a 600 MHz internal clock if an external AC power is supplying energy, and it multiplies the 100 MHz clock by five times to produce a 500 MHz clock if a battery is supplying electric energy.
Since power consumption of a CPU is proportional to the speed of a clock driving the CPU, if a 500 MHz internal clock is used in a battery supplying mode, processing speed is lowered and power dissipation is decreased in comparison to application of a 600 MHz internal clock. Therefore, battery life is extended in a battery supplying mode.
In addition, a clock throttling method is also used to reduce power consumption in a CPU. FIG. 2 shows a clock throttling method in which a clock source is periodically made inactive by a control signal ‘STPCLK#’. Whenever the control signal ‘STPCLK#’, which is active LOW, is in active state, a CPU clock is deactivated, so that the CPU dissipates little power. As a result, average power consumption by the CPU is reduced. Therefore, power consumption reduction rate of a CPU can be regulated through adjustment of a duty cycle of the control signal ‘STPCLK#’.
In related art portable computers configured and operated as above, the performance of a CPU is decreased during a battery supplying mode to reduce power consumption. However, the related art portable computers described above have various disadvantages. A host bus 3 to which both the CPU 11 and the bridge controller 12 are connected is driven by a bus clock, whose speed is fixed and whose state is always active, regardless of the power supplying mode. As a result, all devices connected to the host bus 3 are being driven at all times. Therefore, power saving in a battery supplying mode is less effective than if power was also managed for devices connected to the host bus 3.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.